Pure 8 bit simple instruction set architecture v1.1
Order of priorities:
OverviewHarvard architecture memories:
Flash based progmem space, 256 bytes. Program instructions and constant data are read from here.
Data space, 256 bytes. Containing memory mapped IO and peripherals and also SRAM general purpose volatile data storage.
Hardware registers:8 general registers in two banks.
5 named registers:
Metadata flags:
Instruction anatomy
|
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | ||
0 | 24 | opc | |||||||
1 | 14 | opc | Rr | ||||||
2 | 6 | opc | Rd | Rr | |||||
3 | 2 | opc | i3 | ||||||
4 | 1 | opc | i5 |
Instructions
fmt data name operands description program control 0 RSET Clear PC and SP. Performs a soft reset. 0 1 JUMP I Write immediate to PC 0 1 CALL I Push PC, write immediate to PC 0 RETN Pop PC 0 SAVE Push MF, RB0 R0-R3 and then zero them 0 RSTR Pop RB0 R3-R0, MF 0 TGCF Toggle C flag 0 TGBF Toggle B flag 1 PUSH Rr Copy Rr to @SP-1 and decrement SP 1 POP Rr Copy @SP to Rr and increment SP 4 RJMP i6 Increment PC by i6 signed value (from -32 to +31) 0 NOP Do nothing for 1 clock (RJMP 0) 0 HALT Halt and process no other instructions (RJMP -1) conditionals *skip one instruction if false 0 IFEQ True if Z is set. 0 1 IFNE True if Z is cleared. 0 1 IFLT True if V is set and Z is cleared. 0 IFGT True if V and Z are cleared. 0 IFLE True if V or Z are set. 0 IFGE True if V is cleared or Z is set. 0 1 IFBS i5,i3 True if bit i3 at data address i5 is set 0 1 IFBC i5,i3 True if bit i3 at data address i5 is clear 1 IFR Rr Decrement Rr. True if Rr is non 0. 0 IFC Copy V to C. True if C is set. 0 IFNC Copy V to C. True if C is clear. data movement 0 1 BS i5,i3 set bit i3 at data address i5 0 1 BC i5,i3 clear bit i3 at data address i5 0 1 BWZ i5,i3 write Z to bit i3 at data address i5 0 1 BWV i5,i3 write V to bit i3 at data address i5 1 1 LDR Rr,I Copy I to Rr 3 LDI i3 Copy i + 1 (1-8) to IM 3 x LDD i3,Ix Copy 2^i bytes from @PC to @DP 1 IN Rr Copy @DP to Rr, then INC DP 1 OUT Rr Copy Rr to @DP, then INC DP 1 RBCP Rr Replace Rr with Rr from alternate register bank 1 CLR Rr Zero the value in Rr arithmetic 2 ADD Rd,Rr Add Rr to Rd, replace Rd with result 2 SUB Rd,Rr Subtract Rr from Rd, replace Rd with result 2 CPR Rd,Rr Compare Rr to Rr (subtract) and update MF 2 AND Rd,Rr Bitwise AND 2 IOR Rd,Rr Bitwise inclusive-OR 2 EOR Rd,Rr Bitwise exclusive-OR 1 NOT Rr One's complement (0xFF - Rr) 1 NEG Rr Two's complement (0x00 - Rr) 1 INC Rr Increment by 1 1 DEC Rr Decrement by 1 1 SHL Rr Shift left 1 SHR Rr Shift right
fmt | data | name | operands | description |
program control | ||||
0 | RSET | Clear PC and SP. Performs a soft reset. | ||
0 | 1 | JUMP | I | Write immediate to PC |
0 | 1 | CALL | I | Push PC, write immediate to PC |
0 | RETN | Pop PC | ||
0 | SAVE | Push MF, RB0 R0-R3 and then zero them | ||
0 | RSTR | Pop RB0 R3-R0, MF | ||
0 | TGCF | Toggle C flag | ||
0 | TGBF | Toggle B flag | ||
1 | PUSH | Rr | Copy Rr to @SP-1 and decrement SP | |
1 | POP | Rr | Copy @SP to Rr and increment SP | |
4 | RJMP | i6 | Increment PC by i6 signed value (from -32 to +31) | |
0 | NOP | Do nothing for 1 clock (RJMP 0) | ||
0 | HALT | Halt and process no other instructions (RJMP -1) | ||
conditionals *skip one instruction if false | ||||
0 | IFEQ | True if Z is set. | ||
0 | 1 | IFNE | True if Z is cleared. | |
0 | 1 | IFLT | True if V is set and Z is cleared. | |
0 | IFGT | True if V and Z are cleared. | ||
0 | IFLE | True if V or Z are set. | ||
0 | IFGE | True if V is cleared or Z is set. | ||
0 | 1 | IFBS | i5,i3 | True if bit i3 at data address i5 is set |
0 | 1 | IFBC | i5,i3 | True if bit i3 at data address i5 is clear |
1 | IFR | Rr | Decrement Rr. True if Rr is non 0. | |
0 | IFC | Copy V to C. True if C is set. | ||
0 | IFNC | Copy V to C. True if C is clear. | ||
data movement | ||||
0 | 1 | BS | i5,i3 | set bit i3 at data address i5 |
0 | 1 | BC | i5,i3 | clear bit i3 at data address i5 |
0 | 1 | BWZ | i5,i3 | write Z to bit i3 at data address i5 |
0 | 1 | BWV | i5,i3 | write V to bit i3 at data address i5 |
1 | 1 | LDR | Rr,I | Copy I to Rr |
3 | LDI | i3 | Copy i + 1 (1-8) to IM | |
3 | x | LDD | i3,Ix | Copy 2^i bytes from @PC to @DP |
1 | IN | Rr | Copy @DP to Rr, then INC DP | |
1 | OUT | Rr | Copy Rr to @DP, then INC DP | |
1 | RBCP | Rr | Replace Rr with Rr from alternate register bank | |
1 | CLR | Rr | Zero the value in Rr | |
arithmetic | ||||
2 | ADD | Rd,Rr | Add Rr to Rd, replace Rd with result | |
2 | SUB | Rd,Rr | Subtract Rr from Rd, replace Rd with result | |
2 | CPR | Rd,Rr | Compare Rr to Rr (subtract) and update MF | |
2 | AND | Rd,Rr | Bitwise AND | |
2 | IOR | Rd,Rr | Bitwise inclusive-OR | |
2 | EOR | Rd,Rr | Bitwise exclusive-OR | |
1 | NOT | Rr | One's complement (0xFF - Rr) | |
1 | NEG | Rr | Two's complement (0x00 - Rr) | |
1 | INC | Rr | Increment by 1 | |
1 | DEC | Rr | Decrement by 1 | |
1 | SHL | Rr | Shift left | |
1 | SHR | Rr | Shift right |
Compromises
Implicit registers.
Several instructions work with a general register without explicitly addressing it. The P register is intended to contain a RAM pointer which can be manipulated by normal register arithmetic and then implicitly written through to the address pointed at. The I register is used by just one instruction. LDI is the only single word instruction that supplies a general purpose immediate value. It's only 3 bits of data but that is sufficient for many arithmetic situations.
Register banks.
Limited instruction space and word size severely impact register addressing. Splitting the eight general registers into two banks allows for sufficient register pair instructions. Most instructions are not register bank aware. Arithmetic can't be done on DP while RB1 is selected but it is still correctly incremented by instructions that do. Two instructions affect the B flag, TGBF and RBCP.
Loading direct.
LDD allows for efficient loading of immediate data into RAM in bulk quantities. This should mitigate the limitation that the program counter(PC) is the only method of addressing progmem ROM.
Multi byte arithmetic.
There are no carry versions of relevant arithmetic instructions. In their place the existing instructions have binary behaviour based on the state of the C flag. Default behaviour is to ignore the V flag but still set it appropriately after the operation.
Three instructions affect the C flag: IFC, IFNC and TGCF. For example IFC can be used to bypass unneccessary read/modfy/write of subsequent bytes in a large number.
Direct bit addressing.
To allow bit level access to a reasonable amount of data space, bit operations use 2 instruction words, an 8 bit op code and an 8 bit address. There is no support for programatically addressed bits.
Loop Shortcut.
IFR provides for faster loop termination if the limited circumstances it supports are suitable. It does a decrement, test and branch with a single instruction word. It replaces what would otherwise be 3 instructions.
No Multiplier.
(except for shift)
No barrel shift
and generally rather limited shift capability. The two available shift instructions do support the carry enable flag.

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