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pure 8 bit ISA

Pure 8 bit simple instruction set architecture v1.1

Order of priorities:
  • * strict 8 bit operation including...
    • instruction word
    • memory busses and addresses
    • registers
  • * approachable instruction set with easy, obvious instructions
  • * code density
  • * least die area
  • * maybe C language support (with non-standard 8bit integer)


Harvard architecture memories:
Flash based progmem space, 256 bytes.  Program instructions and constant data are read from here.
Data space, 256 bytes. Containing memory mapped IO and peripherals and also SRAM general purpose volatile data storage.
  • bit-addressable region: bytes 0 - 32 (256 bits)

Hardware registers:

8 general registers in two banks.
  • RB0 R0-R3 register bank 0, four registers, 2 bit addressing
  • RB1 R0-R3 register bank 1, four registers, 2 bit addressing

5 named registers:

  • PC address of the next progmem fetch
  • SP stack pointer
  • MF metadata flags
  • DP implicit pointer. Alias of RB0R0. Used by LDD, IN and OUT
  • IM implicit immediate input. Alias of R1. Used by LDI

Metadata flags:
  • V: Overflow occurred in previous arithmetic instruction.
  • C: Carry enable.  Arithemetic will use V as carry input while C is set.
  • Z: Result of previous arithmetic instruction was zero.
  • B: Register bank select

Instruction anatomy

47 instructions:
  • 13 program control
  • 11 conditionals
  • 11 data movement
  • 12 arithmetic
8 bit instruction word containing:  
2-8 bit opcode
0-2 2 bit register addresses
optionally followed by:
1 or many bytes containing constant data


    7 6 5 4 3 2 1 0
0 24 opc
1 14 opc Rr
2 6 opc Rd Rr
3 2 opc i3
4 1 opc i5


 program control
0 RSET Clear PC and SP. Performs a soft reset.
01JUMPIWrite immediate to PC
01CALLIPush PC, write immediate to PC
0 SAVE Push MF, RB0 R0-R3 and then zero them
0 RSTR Pop RB0 R3-R0, MF
0 TGCF Toggle C flag
0 TGBF Toggle B flag
1 PUSH RrCopy Rr to @SP-1 and decrement SP
1 POP RrCopy @SP to Rr and increment SP
4 RJMP i6Increment PC by i6 signed value (from -32 to +31)
0 NOP Do nothing for 1 clock (RJMP 0)
0 HALT Halt and process no other instructions (RJMP -1) 
 conditionals *skip one instruction if false
0 IFEQ True if Z is set.
01IFNE True if Z is cleared.
01IFLT True if V is set and Z is cleared.
0 IFGT True if V and Z are cleared.
0 IFLE True if V or Z are set.
0 IFGE True if V is cleared or Z is set.
01IFBSi5,i3True if bit i3 at data address i5 is set
01IFBCi5,i3True if bit i3 at data address i5 is clear
1 IFRRrDecrement Rr. True if Rr is non 0.
0 IFC Copy V to C. True if C is set.
0 IFNC Copy V to C. True if C is clear.
 data movement
01BSi5,i3set bit i3 at data address i5
01BC i5,i3clear bit i3 at data address i5
01BWZi5,i3write Z to bit i3 at data address i5
01BWVi5,i3write V to bit i3 at data address i5
11LDRRr,ICopy I to Rr
3 LDI i3Copy i + 1 (1-8) to IM
3xLDDi3,IxCopy 2^i bytes from @PC to @DP
1 INRrCopy @DP to Rr, then INC DP
1 OUTRrCopy Rr to @DP, then INC DP
1 RBCPRrReplace Rr with Rr from alternate register bank
1 CLRRrZero the value in Rr
2 ADDRd,RrAdd Rr to Rd, replace Rd with result
2 SUBRd,RrSubtract Rr from Rd, replace Rd with result
2 CPRRd,RrCompare Rr to Rr (subtract) and update MF
2 ANDRd,RrBitwise AND
2 IORRd,RrBitwise inclusive-OR
2 EORRd,RrBitwise exclusive-OR
1 NOTRrOne's complement (0xFF - Rr)
1 NEGRrTwo's complement (0x00 - Rr)
1 INCRrIncrement by 1
1 DECRrDecrement by 1
1 SHLRrShift left
1 SHRRrShift right


Implicit registers.

Several instructions work with a general register without explicitly addressing it. The P register is intended to contain a RAM pointer which can be manipulated by normal register arithmetic and then implicitly written through to the address pointed at.  The I register is used by just one instruction. LDI is the only single word instruction that supplies a general purpose immediate value.  It's only 3 bits of data but that is sufficient for many arithmetic situations.

Register banks.

Limited instruction space and word size severely impact register addressing.  Splitting the eight general registers into two banks allows for sufficient register pair instructions.  Most instructions are not register bank aware. Arithmetic can't be done on DP while RB1 is selected but it is still correctly incremented by instructions that do.
Two instructions affect the B flag, TGBF and RBCP.

Loading direct.

LDD allows for efficient loading of immediate data into RAM in bulk quantities. This should mitigate the limitation that the program counter(PC) is the only method of addressing progmem ROM.

Multi byte arithmetic.

There are no carry versions of relevant arithmetic instructions.  In their place the existing instructions have binary behaviour based on the state of the C flag. Default behaviour is to ignore the V flag but still set it appropriately after the operation.

Three instructions affect the C flag: IFC, IFNC and TGCF.  For example IFC can be used to bypass unneccessary read/modfy/write of subsequent bytes in a large number.

Direct bit addressing.

To allow bit level access to a reasonable amount of data space, bit operations use 2 instruction words, an 8 bit op code and an 8 bit address.
There is no support for programatically addressed bits.

Loop Shortcut.

IFR provides for faster loop termination if the limited circumstances it supports are suitable. It does a decrement, test and branch with a single instruction word. It replaces what would otherwise be 3 instructions.

No Multiplier.

(except for shift)

No barrel shift

and generally rather limited shift capability.  The two available shift instructions do support the carry enable flag.

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